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ISL43410
Data Sheet January 16, 2006 FN6044.3
Low-Voltage, Single Supply, DPDT High Performance Analog Switch
The Intersil ISL43410 is a precision, bidirectional, analog switch configured as a double pole/double throw (DPDT) switch. The ISL43410 is designed to operate from a single +2V to +12V supply. It is equipped with an inhibit pin to simultaneously open all signal paths. ON resistance is 115 with a +5V supply, 45 with a +12V supply, and 190 with a +3V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 1nA at 25C or 2.5nA at 85C. All digital inputs have 0.8V to 2.4V logic thresholds ensuring TTL/CMOS logic compatibility when using a single +5V supply. Some of the smallest packages are available, alleviating board space limitations, and making Intersil's newest line of low-voltage switches an ideal solution. The ISL43410 is a DPDT, which is perfect for use in 2-to-1 multiplexer applications. Table 1 summarizes the performance of this switch.
TABLE 1. FEATURES AT A GLANCE CONFIGURATION 12V RON 12V tON/tOFF 4.5V RON 4.5V tON/tOFF 3V RON 3V tON/tOFF Packages DPDT 45 25ns/24ns 115 60ns/30ns 190 120ns/45ns 10 Ld MSOP, 16 Ld QFN 3x3
Features
* Fully Specified at 3V, 5V, and 12V Supplies for 10% Tolerances * ON Resistance (RON), VS = 5V . . . . . . . . . . . . . . . . 100 * RON Matching Between Channels . . . . . . . . . . . . . . . . . <2 * Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . 3pC (Max) * Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V * Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . . .<3W * Low Off Leakage Current . . . . . . . . . . . . . . . . . . . . . 2.5nA * Fast Switching Action (VS = 5V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns * Guaranteed Break-Before-Make * TTL, CMOS Compatible * Available in 10 Ld MSOP and 16 Ld QFN Packages * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Battery Powered, Handheld, and Portable Equipment * Communications Systems - Radios - Telecom Infrastructure - ADSL, VDSL Modems * Test Equipment - Medical Ultrasound - Electrocardiograph - Magnetic Resonance Image - CT and PET Scanners (MRI) - ATE * Audio and Video Switching * Various Circuits - +3V/+5V DACs and ADCs - Sample and Hold Circuits - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset Circuits
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches" * Application Note AN520 "CMOS Analog Multiplexers and Switches; Specifications and Application Considerations. * Application Note AN1034 "Analog Switch and Multiplexer Applications"
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2004, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL43410 Pinouts
(Note 1) ISL43410 (MSOP) TOP VIEW
NO1 1 COM1 2 NC1 3 INH 4 GND 5 LOGIC 10 V+ 9 COM2 8 NO2 7 NC2 6 ADD N.C. N.C. N.C. NO1 1 2 3 4 5 COM1 6 NC1 7 INH 8 GND
ISL43410 (QFN) TOP VIEW
COM2 NO2 14 NC2 13 12 ADD 11 N.C. 10 N.C. 9 N.C. V+ 16
15
NOTE: 1. Switches Shown for Logic "0" Inputs.
Truth Table
ISL43410 INH 1 0 0 NOTE: 11V. ADD X 0 1 SWITCH ON NONE NCX NOX
Ordering Information
PART NO. ISL43410IU ISL43410IU-T ISL43410IUZ (Note) ISL43410IUZ-T (Note) FUNCTION ISL43410IR ISL43410IR-T ISL43410IRZ (Note) ISL43410IRZ-T (Note) PART MARKING 3410 3410 3410Z 3410Z TEMP. RANGE (C) PACKAGE PKG. DWG. # M10.118 M10.118 M10.118 M10.118
-40 to 85 10 Ld MSOP -40 to 85 10 Ld MSOP Tape & Reel -40 to 85 10 Ld MSOP (Pb-free) -40 to 85 10 Ld MSOP Tape & Reel (Pb-free) -40 to 85 16 Ld QFN -40 to 85 16 Ld QFN Tape & Reel -40 to 85 16 Ld QFN (Pb-free) -40 to 85 16 Ld QFN Tape & Reel (Pb-free)
Logic "0" 0.8V. Logic "1" 2.4V, with VS between 3.3V and
Pin Descriptions
PIN V+ GND INH COM NO NC ADD N.C. System Power Supply Input (+2V to +12V) Ground Connection Digital Control Input. Connect to GND for Normal Operation. Connect to V+ to turn all switches off. Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin Address Input Pin No Internal Connection
410I 410I 341Z 341Z
L16.3X3 L16.3X3 L16.3X3 L16.3X3
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN6044.3 January 16, 2006
ISL43410
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V Input Voltages INH, NO, NC, ADD (Note 2) . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 40mA
Thermal Information
Thermal Resistance (Typical) JA (C/W) 10 Ld MSOP Package (Note 3) . . . . . . . . . . . . . . . . 190 16 Ld QFN Package (Note 4). . . . . . . . . . . . . . . . . . 62 Maximum Junction Temperature (Plastic Package). . . . . . . . 150C Moisture Sensitivity (See Technical Brief TB363) All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Storage Temperature Range . . . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C (MSOP - Lead Tips Only)
Operating Conditions
Temperature Range ISL43410IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 2. Signals on NC, NO, COM, ADD, or INH exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications +5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (C) Full (NOTE 6) MIN 0 -1 -2.5 -1 -2.5 -1 -5 2.4 -0.5 5 TYP 115 1 12 13 1.4 1.3 60 30 61 16 (NOTE 6) MAX UNITS V+ 125 150 3 5 13 18 1 2.5 1 2.5 1 5 0.8 0.5 65 80 35 40 70 85 V nA nA nA nA nA nA V V A ns ns ns ns ns ns ns
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON RON Matching Between Channels, RON RON Flatness, RFLAT(ON) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF) COM ON Leakage Current, ICOM(ON)
V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V, (See Figure 5) V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V, (Note 8) V+ = 5.5V, ICOM = 1.0mA, VNO or VNC = 1.5V, 2.5V, 3.5V, (Note 9) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V, (Note 7) V+ = 5.5V, VCOM = 4.5V, 1V, VNO or VNC = 1V, 4.5V, (Note 7) V+ = 5.5V, VCOM = 1V, 4.5V, or VNO or VNC = 1V, 4.5V, or Floating, (Note 7)
25 Full 25 Full 25 Full 25 Full 25 Full 25 Full Full Full
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH Input Voltage Low, VINL Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON Inhibit Turn-OFF Time, tOFF Address Transition Time, tTRANS Break-Before-Make Time Delay, tD V+ = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF, VIN = 0 to 3, (See Figure 1) V+ = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF, VIN = 0 to 3, (See Figure 1) V+ = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF, VIN = 0 to 3, (See Figure 1) V+ = 5.5V, RL = 300, CL = 35pF, VNO = VNC = 3V, VIN = 0 to 3, (See Figure 3) 25 Full 25 Full 25 Full Full V+ = 5.5V, VIN = 0V or V+
Full
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FN6044.3 January 16, 2006
ISL43410
Electrical Specifications +5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified (Continued) TEST CONDITIONS CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) RL = 50, CL = 5pF, f = 1MHz, (See Figure 4) RL = 50, CL = 5pF, f = 1MHz, (See Figure 6) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) TEMP (C) 25 25 25 25 25 25 Full V+ = 5.5V, VIN = 0V or V+, all channels on or off Full (NOTE 6) MIN 2 -1 TYP 0.3 75 -85 4 6 12 0.0001 (NOTE 6) MAX UNITS 1 12 1 pC dB dB pF pF pF V A
PARAMETER Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel) NO or NC OFF Capacitance, COFF COM ON Capacitance, CCOM(ON) Power Supply Range Positive Supply Current, I+ NOTES: 5. VIN = input voltage to perform proper function.
COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) POWER SUPPLY CHARACTERISTICS
6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25C. 8. RON = RON (MAX) - RON (MIN). 9. Flatness is defined as the difference between the maximum and minimum value of on-resistance over the specified analog signal range.
Electrical Specifications +3V Supply
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VAH = 2.4V, VAL= 0.8V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (C) Full (NOTE 6) MIN 0 -1 -2.5 -1 -2.5 -1 -5 2.0 -0.5 15 TYP 190 1 48 1.0 0.8 144 53 145 35 (NOTE 6) MAX UNITS V+ 220 250 3 5 90 90 1 2.5 1 2.5 1 5 0.5 0.5 155 175 60 65 160 190 V nA nA nA nA nA nA V V A ns ns ns ns ns ns ns
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON RON Matching Between Channels, RON RON Flatness, RFLAT(ON) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF) COM ON Leakage Current, ICOM(ON)
V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 1.5V, (See Figure 5) V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 1.5V, (Note 8) V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 0.5V, 1.5V, (Note 9) V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 3V, 1V, (Note 7) V+ = 3.6V, VCOM = 3V, 1V, VNO or VNC = 1V, 3V, (Note 7) V+ = 3.6V, VCOM = 1V, 3V, or VNO or VNC = 1V, 3V, or floating, (Note 7)
25 Full 25 Full 25 Full 25 Full 25 Full 25 Full Full Full
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH Input Voltage Low, VINL Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON Inhibit Turn-OFF Time, tOFF Address Transition Time, tTRANS Break-Before-Make Time Delay, tD V+ = 2.7V, VNO or VNC = 1.5V, RL = 300, CL = 35pF, VIN = 0 to 3, (See Figure 1) V+ = 2.7V, VNO or VNC = 1.5V, RL = 300, CL = 35pF, VIN = 0 to 3, (See Figure 1) V+ = 2.7V, VNO or VNC = 1.5V, RL = 300, CL = 35pF, VIN = 0 to 3, (See Figure 1) V+ = 3.6V, RL = 300, CL = 35pF, VNO or VNC = 1.5V, VIN = 0 to 3, (See Figure 3) 25 Full 25 Full 25 Full Full V+ = 3.6V, VIN = 0V or V+
Full
4
FN6044.3 January 16, 2006
ISL43410
Electrical Specifications +3V Supply
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VAH = 2.4V, VAL= 0.8V (Note 5), Unless Otherwise Specified (Continued) TEST CONDITIONS CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) RL = 50, CL = 5pF, f = 1MHz, (See Figure 4) RL = 50, CL = 5pF, f = 1MHz, (See Figure 6) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) V+ = 3.6V, VIN = 0V or V+, all channels on or off TEMP (C) 25 25 25 25 25 25 Full (NOTE 6) MIN -1 TYP 0.5 75 -85 4 6 12 0.0001 (NOTE 6) MAX UNITS 1 1 pC dB dB pF pF pF A
PARAMETER Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel) NO or NC OFF Capacitance, COFF COM ON Capacitance, CCOM(ON) Positive Supply Current, I+
COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) POWER SUPPLY CHARACTERISTICS
Electrical Specifications + 12V Supply
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON RON Matching Between Channels, RON RON Flatness, RFLAT(ON) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF) COM ON Leakage Current, ICOM(ON) Input Voltage High, VINH Input Voltage Low, VINL Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON Inhibit Turn-OFF Time, tOFF Address Transition Time, tTRANS Break-Before-Make Time Delay, tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel) NO or NC OFF Capacitance, COFF COM ON Capacitance, CCOM(ON) Positive Supply Current, I+
Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (C) Full (NOTE 6) MIN 0 -1 -2.5 -1 -2.5 -1 -5 2.9 -0.5 3 -1 TYP 45 0.5 5 2.5 2.3 25 24 35 9 1.2 75 -85 4 6 12 0.0001 (NOTE 6) MAX UNITS V+ 50 70 3 5 6 10 1 2.5 1 2.5 1 5 0.8 0.5 30 35 28 30 50 55 3 1 V nA nA nA nA nA nA V V A ns ns ns ns ns ns ns pC dB dB pF pF pF A
V+ = 12.0V, ICOM = 1.0mA, VNO or VNC = 9V, (See Figure 5) V+ = 12.0V, ICOM = 1.0mA, VNO or VNC = 9V, (Note 8) V+ = 13.2V, ICOM = 1.0mA, VNO or VNC = 3V, 6V, 9V, (Note 9) V+ = 13.0V, VCOM = 1V, 12V, VNO or VNC = 12V, 1V, (Note 7) V+ = 13.0V, VCOM = 12V, 1V, VNO or VNC = 1V, 12V, (Note 7) V+ = 13.0V, VCOM = 1V, 12V, VNO or VNC = 1V, 12V, or floating, (Note 7)
25 Full 25 Full 25 Full 25 Full 25 Full 25 Full Full Full
DIGITAL INPUT CHARACTERISTICS
V+ = 13V, VIN = 0V or V+ V+ = 10.8V, VNO or VNC = 10V, RL = 300, CL = 35pF, VIN = 0 to 4, (See Figure 1) V+ = 10.8V, VNO or VNC = 10V, RL = 300, CL = 35pF, VIN = 0 to 4, (See Figure 1) V+ = 10.8V, VNO or VNC = 10V, RL = 300, CL = 35pF, VIN = 0 to 4, (See Figure 1) V+ = 13.0V, RL = 300, CL = 35pF, VNO or VNC = 10V, VIN = 0 to 4, (See Figure 3) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) RL = 50, CL = 5pF, f = 1MHz, (See Figure 4) RL = 50, CL = 5pF, f = 1MHz, (See Figure 6) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) V+ = 13.0V, VIN = 0V or V+, all channels on or off
Full 25 Full 25 Full 25 Full Full 25 25 25 25 25 25 Full
COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) POWER SUPPLY CHARACTERISTICS
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FN6044.3 January 16, 2006
ISL43410 Test Circuits and Waveforms
3V LOGIC INPUT 0V tON V+ NC NO VOUT INH GND LOGIC INPUT tOFF ADD RL 300 CL 35pF COM VOUT 50% tr < 20ns tf < 20ns C V+ C
90% SWITCH OUTPUT 0V
90%
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS
3V LOGIC INPUT 0V tTRANS 50%
tr < 20ns tf < 20ns
C
V+
C
V+
NC NO COM VOUT
SWITCH OUTPUT 0V tTRANS
90%
VOUT
90% LOGIC INPUT
ADD GND INH RL 300 CL 35pF
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1D. ADDRESS TEST CIRCUIT
FIGURE 1C. ADDRESS MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
V+
C
3V LOGIC INPUT OFF ON 0V OFF RG NO or NC ADD VOUT VG GND INH LOGIC INPUT Q = VOUT x CL CL COM VOUT
SWITCH OUTPUT VOUT
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION
FIGURE 2B. TEST CIRCUIT
6
FN6044.3 January 16, 2006
ISL43410 Test Circuits and Waveforms (Continued)
V+ tr < 20ns tf < 20ns V+ 0V
NC
C
C
3V LOGIC INPUT
NO
COM
VOUT RL 300 CL 35pF
SWITCH OUTPUT VOUT 0V tD
80% LOGIC INPUT
ADD GND INH
Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE TIME FIGURE 3B. TEST CIRCUIT
V+ C SIGNAL GENERATOR
NO OR NC
V+ C RON = V1/1mA
NO OR NC
VNX 0V or V+ ADD 0V or V+ GND INH
COM
1mA
V1
0V OR V+ ADD
ANALYZER RL
COM
GND
INH
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. RON TEST CIRCUIT
V+ C
V+ C
SIGNAL GENERATOR
50
NO1 OR NC1 COM1
NO OR NC
0V OR V+ 0V OR V+ ADD IMPEDANCE ANALYZER
NO2 OR NC2
ADD
NC
COM
ANALYZER RL
COM2
GND
INH
GND
INH
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
7
FN6044.3 January 16, 2006
ISL43410 Detailed Description
The ISL43410 operates from a single 2V to 12V supply with low on-resistance (115) and high speed operation (tON = 60ns, tOFF = 30ns). The ISL43410 is especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2.0V), low power consumption (3W), low leakage currents (5nA max), and the tiny MSOP and QFN packaging. High frequency applications also benefit from the wide bandwidth, and the very high off isolation (75dB) and crosstalk rejection (-85dB).
Power-Supply Considerations
The ISL43410 construction is typical of most CMOS analog switches, except that they have only two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 13V maximum supply voltage, the ISL43410's 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 2.0V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This device cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages.
OPTIONAL PROTECTION RESISTOR FOR LOGIC INPUTS 1k 1k
Logic-Level Thresholds
The ISL43410 is TTL compatible (0.8V and 2.4V) over a supply range of 3V to 11V (see Figure 11). At 12V the VIH level is about 2.5V. This is still below the TTL guaranteed high output minimum level of 2.8V, but noise margin is reduced. For best results with a 12V supply, use a logic family the provides a VOH greater than 3V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails (see Figure 12). Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. The ISL43410 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example driving the device with 3V logic (0V to 3V) while operating with a 5V supply the device draws only 10A of current (see Figure 12 for VIN = 3V). Similar devices of competitors can draw 8 times this amount of current.
OPTIONAL PROTECTION DIODE ADD IN VNO OR NC VCOM V+
High-Frequency Performance
In 50 systems, signal response is reasonably flat even past 100MHz (see Figure 17). Figure 17 also illustrates that the frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch's input to its output. Off Isolation is the resistance to this feed through, while Crosstalk indicates the amount of feed through from one switch to another. Figure 18 details the high Off Isolation and Crosstalk rejection provided by this family. At 10MHz, Off Isolation is about 55dB in 50 systems, decreasing approximately 20dB
FN6044.3 January 16, 2006
GND OPTIONAL PROTECTION DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
8
ISL43410
per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given
Typical Performance Curves TA = 25C, Unless Otherwise Specified
500
VCOM = (V+) - 1V ICOM = 1mA 225 200 175 150 125 100 RON () 75 140 120 100 80 60 80 70 85C 60 50 40 -40C 30 0 85C 25C -40C 25C V+ = 12V V+ = 5V 85C 25C -40C V+ = 3.3V ICOM = 1mA
400
300
RON ()
200
85C 25C
100
-40C
0 2 3 4 5 6 7 8 V+ (V) 9 10 11 12 13
2
4
6 VCOM (V)
8
10
12
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
3.0 2.5 2.0 25C 1.5 VINH AND VINL (V) 1.0 ICC (A) 0.5 3.0 2.5 2.0 1.5 1.0 0.5 2 3 85C 4 5 6 7 8 V+ (V) 9 10 11 12 13 25C VINL -40C 85C VINH -40C
140 V+ = +5V 120 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VIN(ADD) (V)
FIGURE 11. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 12. SUPPLY CURRENT vs DIGITAL ADDRESS INPUT VOLTAGE
9
FN6044.3 January 16, 2006
ISL43410 Typical Performance Curves TA = 25C, Unless Otherwise Specified (Continued)
350 VCOM = (V+) - 1V 300 250 tOFF (ns) tON (ns) 200 150 100 50 0 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 -40C 85C 25C 120 110 100 90 80 70 60 50 40 30 20 10 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 -40C 85C 25C VCOM = (V+) - 1V
FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE
3
350 VCOM = (V+) - 1V 300 250
2 V+ = 12V 1 0 V+ = 5V
200 tTRANS (ns) 150 100 50 0 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 -40C -4 -5 0 2 85C Q (pC) -1 -2 -3
V+ = 3.3V
25C
4
6 VCOM (V)
8
10
12
FIGURE 15. ADDRESS TRANS TIME vs SUPPLY VOLTAGE
FIGURE 16. CHARGE INJECTION vs SWITCH VOLTAGE
-10 10 V+ = 3V to 12V -20 -30 20 30 OFF ISOLATION (dB) 40 50 ISOLATION 60 70 80 CROSSTALK -90 -100 -110 1k 10k 100k 1M 10M 90 100 110 100M 500M
NORMALIZED GAIN (dB)
VIN = 0.2VP-P (V+ = 3V) +3 0 GAIN -3 VIN = 0.2VP-P (V+ = 13V) VIN = 5VP-P (V+ = 13V) 0 PHASE 45 90 135 180 RL = 50 1 10 100 FREQUENCY (MHz) 600 PHASE (DEGREES) CROSSTALK (dB) VIN = 2.5VP-P (V+ = 3V)
-40 -50 -60 -70 -80
FREQUENCY (Hz)
FIGURE 17. FREQUENCY RESPONSE
FIGURE 18. CROSSTALK AND OFF ISOLATION
10
FN6044.3 January 16, 2006
ISL43410 Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 193 PROCESS: Si Gate CMOS
11
FN6044.3 January 16, 2006
ISL43410 Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -BE
INCHES SYMBOL MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120 A
ABC
MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 NOTES 9 3 4 6 7 15o 6o Rev. 0 12/02
INDEX AREA
12 TOP VIEW
0.20 (0.008)
A1 A2
4X
0.25 (0.010) GAUGE PLANE SEATING PLANE -CA A2
R1 R
b c D E1
4X
L L1
e E L L1 N R
0.020 BSC 0.187 0.016 10 0.003 0.003 5o 0o 15o 6o 0.199 0.028
0.50 BSC 4.75 0.40 10 0.07 0.07 5o 0o 5.05 0.70
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
R1
SIDE VIEW
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
12
FN6044.3 January 16, 2006
ISL43410 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
2X A 9 D1 D1/2 6 INDEX AREA N 1 2 3 E1/2 E1 9 2X 0.15 C B 2X 0.15 C A 4X 0 TOP VIEW A2 B E/2 E 2X 0.15 C B D D/2 0.15 C A
L16.3x3
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 1.35 0.20 0.30 e k L N Nd Ne P 1.35 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.23 3.00 BSC 2.75 BSC 1.50 3.00 BSC 2.75 BSC 1.50 0.50 BSC 0.40 16 4 4 0.60 12 0.50 1.65 1.65 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8, 10 9 7, 8, 10 8 2 3 3 9 9 Rev. 1 6/04
A
/ / 0.10 C 0.08 C
C
SEATING PLANE
SIDE VIEW NX b 5
A3
A1
9
4X P D2 (DATUM B) 4X P D2 2N
0.10 M C A B 7 8 NX k
1 (DATUM A) 6 INDEX AREA NX L Ne 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 2 3 E2 7 E2/2 8 (Ne-1)Xe REF.
NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
C L
9 CORNER OPTION 4X
SECTION "C-C" C L
9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation.
L1 e 10 L
L1 CC e
10
L
10. Compliant to JEDEC MO-220VEED-2 Issue C, except for the E2 and D2 MAX dimension.
TERMINAL TIP FOR EVEN TERMINAL/SIDE
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN6044.3 January 16, 2006

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